Regviz

Cypress Semiconductor /psoc63 /SRSS /MCWDT_STRUCT[0] /MCWDT_CTL

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as MCWDT_CTL

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Cypress Semiconductor/psoc63/SRSS/MCWDT_STRUCT[1]/MCWDT_CTL#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDT_ENABLE0)WDT_ENABLE0 0 (WDT_ENABLED0)WDT_ENABLED0 0 (WDT_RESET0)WDT_RESET0 0 (WDT_ENABLE1)WDT_ENABLE1 0 (WDT_ENABLED1)WDT_ENABLED1 0 (WDT_RESET1)WDT_RESET1 0 (WDT_ENABLE2)WDT_ENABLE2 0 (WDT_ENABLED2)WDT_ENABLED2 0 (WDT_RESET2)WDT_RESET2

Description

Multi-Counter Watchdog Counter Control

Fields

WDT_ENABLE0

Enable subcounter 0. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
WDT_ENABLED0

Indicates actual state of counter. May lag WDT_ENABLE0 by up to two LFCLK cycles.
WDT_RESET0

Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
WDT_ENABLE1

Enable subcounter 1. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
WDT_ENABLED1

Indicates actual state of counter. May lag WDT_ENABLE1 by up to two LFCLK cycles.
WDT_RESET1

Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.
WDT_ENABLE2

Enable subcounter 2. May take up to 2 LFCLK cycles to take effect. 0: Counter is disabled (not clocked) 1: Counter is enabled (counting up)
WDT_ENABLED2

Indicates actual state of counter. May lag WDT_ENABLE2 by up to two LFCLK cycles.
WDT_RESET2

Resets counter 0 back to 0000. Hardware will reset this bit after counter was reset. This will take up to one LFCLK cycle to take effect.

Links

()

Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

 ()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data